Conventional analog direct up-converters used in 2.5G/3G transmitters have inherent challenges that degrade output signal quality. Analog IQ mismatches directly contribute to the Error Vector Magnitude (EVM) of the signal, since these up-converters create an image that completely overlaps with that of the desired signal. The analog IQ baseband circuitry also creates DC components at the input of the quadrature direct up-converter, which in turns causes significant local oscillator (LO) feed-through that degrades EVM. Because analog circuits are susceptible to variations in process, voltages, and temperatures, it is difficult to design around such anomalies and it is required to use calibration to minimize these anomalies. Depending on the performance desired, the calibration routine may be a one-time occurrence or a continuous and dynamic process. In addition to the IQ mismatch problems, operating the transmitter LO at the same frequency as the assigned channel of the output signal subjects the synthesizer to “pulling” by the signal that causes frequency error and EVM degradation due to local oscillator (LO) pulling and pushing.
This is detrimental to the ability to isolate between the transmitter LO signal and transmitter output signal from inter-locking, especially since the output signal level after the power amplifier (PA) may easily be as high as 600 mW. As integrated circuit (IC) devices move towards ever smaller line widths, an entirely analog architecture is unable to exploit the advantages of size and power consumption. Smaller line widths also mean lower bias voltages, thereby limiting linearity performance. An entirely analog gain loop limits resolution.
One approach that is now obsolete among wireless terminal application specific integrated circuits (ASICs) is the all analog super-heterodyne architecture, where both up-converter stages are performed in the analog domain. While such an approach benefits from the single sideband (SSB) intermediate frequency-to-radio frequency (IF-RF) up-conversion that separates the carrier LO and the IQ image from the desired signal, it is subject to process, voltage, and temperature variations for both stages of the up-conversion process. This requires a much more complex IQ compensation algorithm for good image rejection. Dynamic IQ calibration is often needed to remove the inter-stage filter. Such an all analog architecture may not be able to benefit from a low line width CMOS process. It requires more silicon than other related solutions and often requires more frequency planning effort than direct up-conversion architectures.
Another architecture that found commercial applications in some narrowband systems (e.g., EDGE) is the Polar Loop architecture. This approach finds several implementations, such as a polar power amplifier (PA) module or an internal polar loop with either a pre-PA driver or a direct up-converter. While such designs offer an elegant technique for achieving a narrowband transmitter and have the original aim of improving efficiency, it is more difficult to use to support broadband signals. One of the difficulties is the timing match-up between the amplitude path and the phase path, both of which are frequency dependent. Techniques have been used to alleviate this issue, but these techniques require a digital pre-PA and introduce spurious images. The tighter the EVM requirement, the more stringent the timing matchup must be. Also, the transmit synthesizer operates at the same frequency as that of the assigned carrier, subjecting it to the same pulling as other designs.
Another type of architecture that is being considered for supporting broadband applications is the Digital-IF architecture using only a single DAC and single channel up-converter. While this architecture takes advantage of digital baseband-to-intermediate frequency (BB-IF) blocks, it requires an inter-stage SAW filter to help suppress the RF image created, because it is unable to provide any image rejection with a single IF-RF up-converter. Given that the image is similar in power to the desired signal, a third-order spurious image is created at the pre-PA driver as well as at the PA if it is not sufficiently suppressed by the inter-stage SAW filter.